This invention relates to first-in-first-out (FIFO) memory devices and more particularly to a display FIFO module that issues requests for display data to a dynamic random access memory (DRAM) controller sequencer which prioritizes DRAM access requests received from various modules.
In a DRAM interface, as shown in FIG. 1, a plurality of modules, including a display FIFO module 12, a CPU 14, a blit engine module 16, a half frame buffer logic module 18, and other modules, such as an nth module 20 are connected to a DRAM controller sequencer 22, which decides which one of the modules should be granted access to a DRAM 24. The blit engine module controls block transfer of bitmap images to, from or within the DRAM. The half frame buffer logic module supports display on a dual scan LCD panel. A DRAM address generator 52 is connected to DRAM controller sequencer 22 and display FIFO module 12. The DRAM address generator generates DRAM addresses to the DRAM controller sequencer. A CRT controller 50 controls DRAM address generator 52 and display pipeline 27. The CRT controller instructs the DRAM address generator when to start loading the FIFO. Display FIFO module 12 is connected between the DRAM controller sequencer 22 and a display pipeline 27 which is connected to a display device 26 such as a cathode ray tube (CRT) or liquid crystal display (LCD). Display FIFO module 12 is used for receiving and storing display data for the display device. When a FIFO in the display FIFO module is used to store display data received from DRAM 24, sometimes FIFO overrun may occur in which new data transferred to the FIFO exceeds its capacity so that some unread data in the FIFO will be overwritten by the new data. Also, FIFO underrun may occur when the FIFO runs out of display data and unintended data will be displayed on the display device. It is imperative to prevent both FIFO overrun and underrun conditions from occurring. At the same time, it is also desirable to improve the efficiency of the interaction between the various modules connected to the DRAM controller sequencer and the display FIFO module. For example, the CPU should not have to wait long for DRAM access while the display FIFO module is being serviced by the DRAM controller sequencer.
In devices such as that shown in FIG. 1, display FIFO module 12 issues a low priority request when the FIFO is ready to accept new data without overwriting unread data. The display FIFO module issues a high priority request when the FIFO must receive new data or FIFO underrun will occur. These requests are granted on a priority basis along with requests from the CPU and BLT engine requests as disclosed and described in U.S. Pat. No. 5,673,416, for example.
In certain prior art devices, due to the nature of the DRAM requests and the priority scheme used, there are long waiting periods during which the CPU has to wait for DRAM access. This results in inefficient CPU operations and slows down the computer system. This problem was addressed in U.S. Pat. No. 5,673,416 by increasing the time during which the low priority request is active. However, this can result in repetitive display FIFO requests as the FIFO data level oscillates around the low priority request threshold with the request being removed as the FIFO is filled above the threshold and then being reasserted as soon as the level drops below the threshold. In low power devices such as "hand-held" PCs, the resulting frequent memory accesses can be a significant power drain.